1. Field of the Invention
The invention relates to semiconductor manufacturing, and more particularly to a damascene structure and process at a semiconductor substrate level.
2. Description of the Related Art
The application of damascene process continues to gain wider acceptance, most notably in the process of copper metallization due to the difficulty of copper dry etch where the damascene plug penetrates deeply into very small, sub-half micron, Ultra Large Scale integrated devices. Even when the use of copper wiring for multilevel interconnects has been demonstrated by dual damascene, tungsten plugs are exclusively used for contact points at substrate level in order to avoid damage to the devices in spite of the lower electrical conductivity. See for example, U.S. Pat. No. 6,211,085 to Chung-Shi Liu.
The aspect ratios of contact holes are rapidly increasing in recent years as the density of integrated circuits increases. With such increasing aspect ratios of contact holes, however, it is believed that tungsten plugs will no longer be desirable for next generation devices due to the increasing contact resistance at deep and narrow contact holes.
Another issue with tungsten plugs is the risk of contact electromigration failure since a dissimilar material such as aluminum or copper is typically used as the first level metal.
Accordingly, there exists a need in the art for an improved architecture for very fine contact holes at substrate level which can provide higher electrical conductivity and improved electromigration resistance. To this end, copper plugs at semiconductor substrate level are proposed.